A Digital Vlsi Low Power Integrated Circuit Architecture for Delay Estimation

The design of a low power digital VLSI CMOS integrated circuit for the measurement of signals in the range [10, 300] Hz is presented. The architecture performs a delay calculation in order to determine the bearing angle of a sound source. Restrictions regarding power dissipation are to be improved against a previous implementation, while keeping computing accuracy. A Verilog RTL preliminary implementation is tested on a Xilinx® FPGA in order to determine performance of the calculation algorithm and tuning-up the digital structure.